The present invention relates to a semiconductor integrated circuit device formed by insulated gate field effect transistors (hereinafter referred to simply as "MOSFET") as main elements and, more particularly, to an electrically erasable programmable ROM (hereinafter referred to as "EEPROM") having a digit line biasing means.
A portion of a prior art read-out circuit of EEPROM is diagrammatically shown in FIG. 7. In the drawings, Y.sub.1, . . . , Y.sub.m are Y-address lines for selecting Y-addresses of memory cells, X.sub.1, . . . , X.sub.n are X-address lines for selecting X-addresses of the memory cells, W.sub.1, . . . , W.sub.n are word lines, Cg is a signal line to which is applied a read-out voltage V.sub.R during the read-out mode, and SS is a common source line of the memory cells, to which the voltage 0 V is applied during the read-out mode.
SENSE is a sense amplifier circuit, REF is a reference circuit, and DIFF is a comparator for comparing an output voltage V.sub.SA of the sense amplifier circuit and an output voltage V.sub.REF of the reference circuit and amplifying a difference therebetween. The output D.sub.o of the DIFF is transferred to an output buffer circuit (not shown). Each of the memory cells off the EEPROM consists of two transistors connected in series and, for example, a memory cell M.sub.11 consists of a selecting cell M.sub.S11 and a memorizing M.sub.M11. Each of other memory cells M.sub.n1, M.sub.1m, M.sub.nm likewise consists of such a selecting cell and such a memorizing cell connected in series. The selecting cells M.sub.S11, M.sub.Sn1, M.sub.S1m, M.sub.Snm are N-channel enhancement type MOSFETs (hereinafter referred to as "NE-MOSFET") and the memorizing cells M.sub.M11, M.sub.Mn1, M.sub.M1m, M.sub.Mnm are MOSFETs having floating gates wherein actual writing-in and erasing of data are effected.
Q.sub.Y1, . . . , Q.sub.Ym are NE-MOSFETs for selecting Y-addresses of the memory cells, Q.sub.Y1B, . . . , Q.sub.YmB are NE-MOSFETs for selecting Y-addresses of the byte, Q.sub.B11, . . . , Q.sub.Bn1, . . . , Q.sub.B1m, . . . , Q.sub.Bnm are NE-MOSFETs for selecting X-addresses of the byte. EEPROM is shown by a portion marked as MX in FIG. 7 and if the EEPROM is to be of an 8-bit output in an actual configuration there will be eight of these but such illustration is omitted.
To simplify the explanation herein, it is assumed that the threshold values of the respective NE-MOSFETs are the same and V.sub.TN in all. FIG. 8 diagrammatically shows a prior art sense amplifier circuit. The portion represented by MX is the same as that shown in FIG. 7 and the explanation therefor is omitted. Q.sub.S1 is an N-channel non-doped MOSFET (hereinafter referred to as "NO-MOSFET") having its gate and its drain commonly connected to the power source CC and its source connected to a node SA. Q.sub.S2 is an NE-MOSFET having its drain connected to the node SA, its gate connected to an output (node SI) of a feedback inverter IV formed by transistors Q.sub.S4 through Q.sub.S7 and its source connected to a node SC. Q.sub.S3 is an NE-MOSFET for pre-charging having its drain connected to the power source CC, its gate connected to the node SI, and its source connected to the node SA. Q.sub.S4 is a P-channel enhancement type MOSFET (hereinafter referred to as "PE-MOSFET") having its source connected to the power source CC, its gate connected to a signal line RD which turns to "L" during the read-out mode. Q.sub.S5 is a PE-MOSFET having its source connected to a drain of Q.sub.S4, its gate grounded and its drain connected to the node SI. Q.sub.S6 is an NE-MOSFET having its drain connected to the node SI, its gate connected to the node SC, and its source grounded. Q.sub.S7 is an NE-MOSFET connected in parallel to Q.sub.S6 and having its gate connected to the signal line RD. SD.sub.1, . . . , SD.sub.m form respective digit lines to which, in the case of a large capacity or large scale EEPROM, a capacitance as large as several picofarads is applied.
The feedback inverter IV is generally designed to have a high gain so that it can amplify at a high speed a voltage change in the digit line which varies according to the memorized content in a selected memory cell. The operation of the sense amplifier circuit shown in FIG. 8 is briefly explained. To simplify the explanation, it is assumed that each of the MOSFETs in the circuit represented by SENSE has a gate-width/gate-length (hereinafter referred to as "W/L") as given hereunder.
(1) W/L of Q.sub.S1 is so designed that this W/L balances with a current IM which flows in a memorizing cell storing "0". It is so designed that when IM=20 .mu.A the voltage at the node SA becomes 8.25 V at the power supply voltage (V.sub.cc) of 5 V. PA1 (2) W/L of each of Q.sub.S2 and Q.sub.S3 is so designed that this W/L is sufficiently large as compared with that of Q.sub.S1. PA1 (3) W/L of each of Q.sub.S4, Q.sub.S5, Q.sub.S6 and Q.sub.7 is so designed that the feedback inverter IV has a high gain.
Consequently, it is assumed that W/L of the transistors involved is designed as, for example, Q.sub.S1 =5/17.5, Q.sub.S2 =20/1.4, Q.sub.S3 =20/1.4, Q.sub.S4 =10/1.8, Q.sub.S5 =5/2, Q.sub.S6 =50/2 and Q.sub.S7 =10/1.4, respectively.
It is also assumed here that M.sub.M11 is storing "1" (erased state) so that, even if this M.sub.M11 is selected and a read-out voltage V.sub.R is applied to the gate thereof, M.sub.M11 becomes non-conductive. Further, it is assumed that M.sub.Mn1 and M.sub.M1m are storing "0" (written-in state) so that, when M.sub.Mn1 or M.sub.M1m is selected and the read-out voltage V.sub.R is applied to the gate thereof, M.sub.MMn1 or M.sub.M1m becomes conductive thereby allowing the current IM to -Flow therein.
[1] The state under which X-address line is changed and the memorizing cell M.sub.Mn1 is selected:
When Y.sub.1 is "H", X.sub.1 turns from "H" to "L" and X.sub.n turns from "L" to "H", the memorizing cell M.sub.n1 is selected. Under this state, Q.sub.Y1 becomes conductive and the digit line SD.sub.1 is coupled to the input (the node SC) of the sense amplifier circuit SENSE. Since both the Q.sub.Y1B and Q.sub.Bn1 become conductive, the read-out voltage V.sub.R is applied to the gate of M.sub.Mn1. As M.sub.Mn1 is storing "0", the current IM flows in the memory cell M.sub.n1 whereby the voltage of the digit line SD.sub.1 slightly drops. Then, this voltage change in the digit line SD.sub.1 is transmitted to the node SC and the voltage at the output node SI of the feedback inverter IV rises, so that Q.sub.S2 becomes conductive and that the current IM flows also therein. Under this state, the voltage at the node SA drops and, as explained above, the voltage at the node SA balances at 3.25 V when the power supply voltage V.sub.cc =5 V. In the following consideration, it is assumed that the voltage at the node SA when the memorizing cell storing "0" is selected is V.sub.SA(on). Further, it is assumed that the balanced voltage at the node (digit line) SD.sub.1 under this state is V.sub.SD1(on). The value of the V.sub.SA(on) is generally shown by the following expression (1): EQU V.sub.SA(on) =V.sub.cc -.alpha. .alpha.&gt;V.sub.TO ( 1)
(V.sub.TO is a threshold voltage of Q.sub.S1 and .alpha. is a voltage difference between the gate and the source of the transistor Q.sub.S1 to cause the current IM to flow).
Since the output voltage V.sub.REF of the reference circuit REF is, as shown in the expression (2), set higher than V.sub.SA(on), "L" is outputted at an output D.sub.o of the comparator DIFF shown in FIG. 7. EQU V.sub.REF &gt;V.sub.SA(on) +.alpha. (2)
(.alpha. is the minimum voltage difference which the comparator DIFF can detect.)
[2] The state under which X-address line is changed and the memory cell M.sub.M11 is selected:
When Y.sub.1 is "H", X.sub.n turns from "H" to "L" and X.sub.1 turns from "L" to "H", the memory cell M.sub.11 is selected. Under this state, Q.sub.Y1, Q.sub.Y1B and Q.sub.S11 become conductive and the node SD.sub.1 is coupled to the node SC, and the read-out voltage V.sub.R is applied to the gate of M.sub.M11. As .sub.M11 is storing "1", M.sub.M11 becomes non-conductive. Thus, the digit line SD.sub.1 and the node SC are charged through Q.sub.S1, Q.sub.S2 and the voltages thereof rise slightly from the equilibrium value V.sub.SD1(on) of the previous cycle, while the voltage at the node SI drops thereby causing Q.sub.S2 to become non-conductive. As a result, the node SA is separated from the node SC and the node SA is charged by Q.sub.S1 and balanced at the V.sub.SA(off) as expressed by the equation (3). Here, the digit line SD.sub.1 and the node SC balance at the equilibrium value V.sub.SD1(off). EQU V.sub.SA(off) =V.sub.cc -V.sub.TO ( 3)
Under this state, assuming that V.sub.TO is 0.5 V and V.sub.cc is 5 V, the value of V.sub.SA(off) is 4.5 V.
Since the reference voltage V.sub.REF is, as shown in the following expression (4), set lower than V.sub.SA(off), "H" is outputted from the output D.sub.o of the comparator DIFF shown in FIG. 7. EQU V.sub.REF &lt;V.sub.SA(off) -.alpha. (4)
Assuming that the value of V.sub.REF is set to a value satisfying the above expressions (2) and (4) and, in this example, is set to .alpha.=0.2 V, the reference circuit REF is designed such that, for example, V.sub.REF =3.85 V.
[3] The state under which Y-address line is changed and the memorizing cell M.sub.M11 is selected:
Next, explained with reference to FIGS. 7 through 9 is the operation which takes place under the state wherein the memorizing cell M.sub.11 is selected with Y.sub.1 turning from "L" to "H" and Y.sub.m turning "H" to "L", which state is changed from the state wherein the memorizing cell M.sub.1m is selected with Y.sub.1 being "L", Y.sub.m being "H", X.sub.m being "H" and X.sub.m being "L", when Y-address lines are switched.
FIG. 9 shows voltage waveforms at the various essential nodes in the case where the power supply voltage V.sub.cc is 5 V. The symbols used in the graph correspond to the respective nodes shown in FIG. 8. The operation which takes place when the digit line SD.sub.1 is rendered to be the ground potential due to such as Junction leakage determines a worst value of the speed of the sense amplifier circuit. The operation under such state will be explained hereunder.
As explained under [2] above, M.sub.M11 is storing "1" and thus M.sub.M11 becomes non-conductive. Therefore, simultaneously with the switching of the Y-address lines, the charge is supplied from the node SC to the digit line SD.sub.1 of the ground potential for charging. Consequently, the potential at the node SC drops slightly. As explained above, since the feedback inverter has a high gain for a high speed operation, the voltage at the node SI rapidly rises when the potential at the node SC turns lower than the equilibrium voltage V.sub.SD1(on). For this reason, Q.sub.S2 becomes conductive and the voltage at the node SA rapidly drops. The voltage at this point is, as shown in FIG. 9, lower than V.sub.SA(on) rendering the node SA to be in an excessively discharged state. Here, since the gate-source voltage differences of Q.sub.S3 and Q.sub.S1 become larger than V.sub.TN and V.sub.TO, respectively, both Q.sub.S3 and Q.sub.S1 become conductive thereby causing the digit line SD.sub.1 and the node SC to be charged through Q.sub.S2. As the node SC and the digit line SD.sub.1 are charged, the voltage at the node SI becomes lower and, when the value of the voltage difference (V.sub.SI -V.sub.SA) between the node SI and the node SA becomes V.sub.TN, Q.sub.S3 turns to non-conductive and, thereafter, the charging is made only by Q.sub.S1. The node SC and the digit line SD.sub.1 are further charged and the voltage at the node SI further drops and when the time reaches t21, Q.sub.S2 becomes non-conductive, so that the node SA is released from the excessively discharged state and is quickly charged by Q.sub.S1. As explained before under [2] above, the node SA rises up to a value as shown in the equation (3) and balances at this value, whereby "H" is outputted from the output D.sub.o of the comparator DIFF shown in FIG. 7. The access time under this state is represented by t.sub.sense2 in FIG. 9.
In the conventional EEPROM which operates as explained above, as there are instances where a non-selected digit line becomes 0 V due to such causes as a junction leakage, when Y-address is switched and the memorizing cell storing "1" is selected, it is necessary for the digit line to be charged from 0 V up to the equilibrium value V.sub.SD1(off). The time required for this time t.sub.ch may be expressed, on the basis that the difference in the voltage to be charged is .DELTA.V, the capacitance of the digit line is C.sub.digit, the average load current to charge the digit line is I.sub.LOAD (the value of I.sub.LOAD being determined by W/L of Q.sub.S1 through Q.sub.S6), by the following equation (5): EQU t.sub.ch =(C.sub.digit .multidot..DELTA.V)/I.sub.LOAD ( 5)
In this conventional example, the value of V.sub.SD1(off) is set slightly higher than the logical threshold value of IV so that, when V.sub.SD1(off) =1.1 V, the difference in the voltage to be charged will be .DELTA.V=V.sub.SD1(off) =1.1 V. Further, C.sub.digit is 2 pF and I.sub.LOAD is 100 .mu.A in this conventional example, the time t.sub.ch required for the necessary charging will be t.sub.ch =22 nS. In an EEPROM, a memory cell is formed by two transistors per cell, so that the current IM which flows in the memorizing cell is generally as small as about 20 .mu.A. Thus, the value of I.sub.LOAD which is set to be balanced with the current IM cannot be set to a large value. As the circuit capacity or circuit scale is made larger, the larger the value of C.sub.digit becomes and, since 1M is substantially determined by W/L of each of the selecting cells and the memorizing cells, it is not possible to achieve the desired improvement by an increase in the circuit scale. As the capacity or scale is increased, there is a trend that the value t.sub.ch shown by the equation (5) increases accordingly.
Under the state in which X-address line is changed, since the voltage at the digit lines is always biased in advance to the equilibrium value (in this example, to the vicinity of 1 V), even if tile capacity is increased and the value of C.sub.digit becomes large, it is possible to have the EEPROM operate at a high speed by making the time constant small with an arrangement, for example, wherein the word lines W.sub.1, . . . , W.sub.n shown in FIG. 8 are formed by low resistance materials.
On the other hand, the speed of the sense amplifier in the state under which Y-address line is changed and the memorizing cell storing "1" is selected is determined by the time t.sub.ch required for charging lip the digit line from 0 V to the equilibrium value, so that it is not possible to increase the speed by any decrease in the time constant for the word lines. Therefore, as the circuit capacity or scale becomes larger, the greater the speed of the EEPROM is restricted by the operation speed of the sense amplifier in which the memorizing cell storing "1" is selected when Y-address line is changed. Thus, in the conventional EEPROM as shown in FIG. 8, it is not possible to achieve a high speed operation if such EEPROM has a large capacity or scale, which is a disadvantage.
In the conventional EEPROM explained above, since there is a state wherein the voltage of non-selected digit line is 0 V thereby necessitating to charge such digit line up to the equilibrium value from 0 V when the Y-address line is changed, so that the greater the capacity or scale is increased the slower the speed for charging becomes, which means that the operating speed of such EEPROM is limited by the time in which the digit line is charged up to the equilibrium value from 0 V. Therefore, a problem therein is that it is not possible to have both the circuit capacity or scale and the speed increased in such conventional EEPROM.